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EL7530
Data Sheet July 12, 2006 FN7434.6
Monolithic 600mA Step-Down Regulator with Low Quiescent Current
The EL7530 is a synchronous, integrated FET 600mA stepdown regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The EL7530 features automatic PFM/PWM mode control, or PWM mode only. The PWM frequency is typically 1.4MHz and can be synchronized up to 12MHz. The typical no load quiescent current is only 120A. Additional features include a Power-Good output, <1A shut-down current, short-circuit protection, and over-temperature protection. The EL7530 is available in the 10 Ld MSOP package, making the entire converter occupy less than 0.18n2 of PCB area with components on one side only. The 10 Ld MSOP package is specified for operation over the full -40C to +85C temperature range.
Features
* Less than 0.18in2 footprint for the complete 600mA converter * Components on one side of PCB * Max height 1.1mm MSOP10 * Power-Good (PG) output * Internally-compensated voltage mode controller * Up to 95% efficiency * <1A shut-down current * 120A quiescent current * Overcurrent and over-temperature protection * External synchronizable up to 12MHz * Pb-free plus anneal available (RoHS compliant)
Applications
* PDA and pocket PC computers * Bar code readers * Cellular phones * Portable test equipment * Li-Ion battery powered devices * Small form factor (SFP) modules
Ordering Information
PART TAPE & PART NUMBER MARKING REEL EL7530IY EL7530IY-T7 EL7530IY-T13 EL7530IYZ (Note) EL7530IYZ-T7 (Note) EL7530IYZ-T13 (Note) BYAAA BYAAA BYAAA BAADA BAADA BAADA 7" 13" 7" 13" PACKAGE 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043
Typical Application Diagram
EL7530 TOP VIEW
VS (2.5V to 5.5V) VIN R3 100 C2 10F C3 0.1F R5 100k PG EN FB R2* 100k VO VDD
EL7530
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
LX
L1 1.8H C1 10F
VO
Pinout
EL7530 (10 LD MSOP) TOP VIEW
1 SGND 2 PGND 3 LX 4 VIN 5 VDD FB 10 VO 9 PG 8 EN 7 SYNC 6 R4 100k R6 100k
R1* 124k
C4 470pF
SYNC
PGND SGND
(1.8V @ 600mA)
* VO = 0.8V * (1 + R1 / R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL7530
Absolute Maximum Ratings (TA = 25C)
VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) MSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . . 115 Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
PARAMETER DC CHARACTERISTICS VFB IFB VIN, VDD VIN,OFF VIN,ON IS
VDD = VIN = VEN = 3.3V, C1 = C2 = 10F, L = 1.8H, VO = 1.8V (as shown in Typical Application Diagram), unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Feedback Input Voltage Feedback Input Current Input Voltage Minimum Voltage for Shutdown Maximum Voltage for Startup Input Supply Quiescent Current Active - PFM Mode Active - PWM Mode
PWM Mode
790
800
810 100
mV nA V V V
2.5 VIN falling VIN rising 2 2.2
5.5 2.2 2.4
VSYNC = 0V VSYNC = 3.3V PWM, VIN = VDD = 5V EN = 0, VIN = VDD = 5V
120 6.5 400 0.1 70 45 1.2
145 7.5 500 1 100 75
A mA A A m m A C C
IDD
Supply Current
RDS(ON)-PMOS
PMOS FET Resistance
VDD = 5V, wafer test only VDD = 5V, wafer test only
RDS(ON)-NMOS NMOS FET Resistance ILMAX TOT,OFF TOT,ON IEN, ISYNC VEN1, VSYNC1 VEN2, VSYNC2 VPG Current Limit Over-temperature Threshold Over-temperature Hysteresis EN, SYNC Current EN, SYNC Rising Threshold EN, SYNC Falling Threshold Minimum VFB for PG, WRT Targeted VFB Value PG Voltage Drop
T rising T falling VEN, VRSI = 0V and 3.3V VDD = 3.3V VDD = 3.3V VFB rising VFB falling ISINK = 3.3mA 86 0.8 -1
145 130 1 2.4
A V V
95
% %
VOLPG
35
70
mV
AC CHARACTERISTICS FPWM tSYNC tSS PWM Switching Frequency Minimum SYNC Pulse Width Soft-start Time Guaranteed by design 1.25 25 650 1.4 1.6 MHz ns s
2
FN7434.6 July 12, 2006
EL7530 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME SGND PGND LX VIN VDD SYNC EN PG VO FB Negative supply for the controller stage Negative supply for the power stage Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage Positive supply for the power stage Power supply for the controller stage SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz Enable Power-Good open drain output Output voltage sense Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output PIN FUNCTION
Block Diagram
100 0.1F
VDD VO 10pF INDUCTOR SHORT + CURRENT SENSE PWM COMPENSATION + PWM COMPARATOR PFM ON-TIME CONTROL CONTROL LOGIC
C4 124K 470pF
VIN
FB
5M
+
100K SYNC EN 10F SYNC EN SOFTSTART CLOCK RAMP GENERATOR
P-DRIVER LX 1.8H 1.8V 0 TO 600mA
+ PWM COMPARATOR UNDERVOLTAGE LOCKOUT TEMPERATURE SENSE POWER GOOD
N-DRIVER
10F
5V + -
BANDGAP REFERENCE
SGND
+ SYNCHRONOUS RECTIFIER
PGND 100K PG PG
3
FN7434.6 July 12, 2006
EL7530 Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
100 95 90 EFFICIENCY (%) 85 EFFICIENCY (%) 80 75 70 65 60 55 50 45 40 1 10 IO (mA) 100 600 VIN=5V VO=1.2V VO=0.8V VO=1.8V VO=1.5V VO=1.0V VO=3.3V VO=2.5V 100 90 80 70 60 50 40 30 20 10 0 1 10 IO (mA) 100 600 VO=3.3V VO=2.5V VO=1.8V VO=1.5V VO=1.2V VO=1.0V VO=0.8V VIN=5V
FIGURE 1. EFFICIENCY vs IO (PFM/PWM MODE)
FIGURE 2. EFFICIENCY vs IO (PWM MODE)
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 45 40 1 10 IO (mA) 100 600 VIN=3.3V VO=1.5V VO=1.2V VO=1.0V VO=0.8V VO=2.5V VO=1.8V EFFICIENCY (%)
100 90 80 70 60 50 40 30 20 10 0 1 10 IO (mA) 100 600 VO=0.8V VIN=3.3V VO=2.5V VO=1.8V VO=1.5V VO=1.2V VO=1.0V
FIGURE 3. EFFICIENCY vs IO (PFM/FWM MODE)
FIGURE 4. EFFICIENCY vs IO (PWM MODE)
1.44 VIN=5V IO=600mA 1.42 1.4
VIN=3.3V IO=600mA VIN=5V IO=0A VO CHANGES
0.1% 0.0% -0.1% -0.2% -0.3% -0.4% -0.5% VIN=5V VIN=3.3V
FS (MHz)
VIN=3.3V IO=0A 1.38 1.36 1.34 1.32 -50
0
50 TA (C)
100
150
0
0.2
0.4 IO (A)
0.6
0.8
1
FIGURE 5. FS vs JUNCTION TEMPERATURE (PWM MODE)
FIGURE 6. LOAD REGULATIONS (PWM MODE)
4
FN7434.6 July 12, 2006
EL7530 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
0.1% 0.0% -0.1% VO CHANGES -0.2% -0.3% -0.4% -0.5% -0.6% -0.7% -50 VIN=5V IO=600mA 0 50 TJ (C) 100 150 2 0 2.5 3 VIN=3.3V IO=600mA IS (mA) VIN=3.3V IO=0A VIN=5V IO=0A 12 10 8 6 4
3.5 VS (V)
4
4.5
5
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs JUNCTION TEMPERATURE
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)
140 130 120 110 IS (A) 100 90 80 70 60 50 2.0 2.5 3.0 3.5 4.0 VS (V) 4.5 5.0 5.5 6.0 VO=1.5V VO=1.2V VO=1.0V VO=0.8V VO=1.8V VO=3.3V
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)
1 VIN (2V/DIV)
2
IIN (0.25A/DIV) VO (2V/DIV) PG
EN
IIN (0.25A/DIV) VO (2V/DIV) PG
200s/DIV
500s/DIV
FIGURE 10. START-UP AT IO = 600mA
FIGURE 11. ENABLE AND SHUT-DOWN
5
FN7434.6 July 12, 2006
EL7530 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
LX (2V/DIV)
LX (2V/DIV) IL (0.5A/DIV)
IL (0.5A/DIV)
VO (50mV/DIV)
VO (10mV/DIV)
2s/DIV
0.5s/DIV
FIGURE 12. PFM STEADY-STATE OPERATION WAVEFORM (IO = 100mA)
FIGURE 13. PWM STEADY-STATE OPERATION (IO = 600mA)
SYNC (2V/DIV) LX (2V/DIV) IL (0.5A/DIV)
SYNC (2V/DIV) LX (2V/DIV) IL (0.5A/DIV)
0.2s/DIV
20ns/DIV
FIGURE 14. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 15. EXTERNAL SYNCHRONIZATION TO 12MHz
IO (200mA/DIV) VO (100mV/DIV)
IO (200mA/DIV) VO (100mV/DIV)
100s/DIV
50s/DIV
FIGURE 16. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
FIGURE 17. PWM LOAD TRANSIENT RESPONSE (30mA TO 600mA)
6
FN7434.6 July 12, 2006
EL7530 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
100 80 EFFICIENCY (%) 60 40 20 0 50s/DIV 5MHz
1.4MHz
12MHz
IO (200mA/DIV)
VO (50mV/DIV)
0
200
400
600 IO (mA)
800
1K
1.2K
FIGURE 18. PWM LOAD TRANSIENT RESPONSE (100mA TO 500mA)
FIGURE 19. EFFICIENCY vs IO (PWM MODE)
1 12MHz 0.6 VO CHANGES (%) 0.2 0 -0.2 -0.6 1.4MHz 5MHz VO CHANGES (%)
0.5 0.3 0.1 1.4MHz -0.1 -0.3 -0.5 5MHz 12MHz
0
200
400
600 IO (mA)
800
1K
1.2K
0
200
400
600 VIN (V)
800
1K
1.2K
FIGURE 20. LOAD REGULATION (PWM MODE)
FIGURE 21. LINE REGULATION @ 500mA (PWM MODE)
IO=150mA SYNC (2V/DIV)
IO=50mA SYNC (2V/DIV)
LX (2V/DIV)
LX (2V/DIV)
2s/DIV
2s/DIV
FIGURE 22. PFM-PWM TRANSITION TIME
FIGURE 23. PFM-PWM TRANSITION TIME
7
FN7434.6 July 12, 2006
EL7530 Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted.
3 2 VO CHANGES (%) 1 0 -1 PFM -2 -3 PWM
0
200
400
600 IOUT (mA)
800
1000
1200
FIGURE 24. PFM-PWM LOAD REGULATION
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) 0.5 0.4
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 POWER DISSIPATION (W) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JA =
870mW
M SO P8 /1 11 0 5 C/ W
486mW
M
0.3 0.2 0.1 0 0 25
JA =
SO P8 /1 20 0 6 C/ W
50
75 85
100
125
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
8
FN7434.6 July 12, 2006
EL7530 Applications Information
Product Description
The EL7530 is a synchronous, integrated FET 600mA stepdown regulator which operates from an input of 2.5V to 5.5V. The output voltage is user-adjustable with a pair of external resistors. When the load is very light, the regulator automatically operates in the PFM mode, thus achieving high efficiency at light load (>70% for 1mA load). When the load increases, the regulator automatically switches over to a voltage-mode PWM operating at nominal 1.4MHz switching frequency. The efficiency is up to 95%. It can also operate in a fixed PWM mode or be synchronized to an external clock up to 12MHz for improved EMI performance. In this mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10F to 22F ceramic and inductor is 1.5H to 2.2H.
PFM Operation
The heart of the EL7530 regulator is the automatic PFM/PWM controller. If the SYNC pin is connected to ground, the regulator operates automatically in either the PFM or PWM mode, depending on load. When the SYNC pin is connected to VIN, the regulator operates in the fixed PWM mode. When the pin is connected to an external clock ranging from 1.6MHz to 12MHz, the regulator is in the fixed PWM mode and synchronized to the external clock frequency. In the automatic PFM/PWM operation, when the load is light, the regulator operates in the PFM mode to achieve high efficiency. The top P channel MOSFET is turned on first. The inductor current increases linearly to a preset value before it is turned off. Then the bottom N channel MOSFET turns on, and the inductor current linearly decreases to zero current. The N channel MOSFET is then turned off, and an antiringing MOSFET is turned on to clamp the VLX pin to VO. The inductor current looks like triangular pulses. The frequency of the pulses is mainly a function of output current. The higher the load, the higher the frequency of the pulses until the inductor current becomes continuous. At this point, the controller automatically changes to PWM operation. When the controller transitions to PWM mode, there can be a perturbation to the output voltage. This perturbation is due to the inherent behavior of switching converters when transitioning between two control loops. To reduce this effect, it is recommended to use the phase-lead capacitor (C4) shown in the Typical Application Diagram on page 1. This capacitor allows the PWM loop to respond more quickly to this type of perturbation. To properly size C4, refer to the Component Selection section.
Forced PWM Mode/SYNC Input
Pulling the SYNC pin HI (>2.5V) forces the converter into PWM mode in the next switching cycle regardless of output current. The duration of the transition varies depending on the output current. Figures 22 and 23 (under two different loading conditions) show the device goes from PFM to PWM mode. Note: In Forced PWM mode, the IC will continue to start-up in PFM mode to support pre-biased load applications.
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The inductor current limit is gradually increased to ensure proper soft-start operation. When the EN pin is connected to a logic low, the EL7530 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1A. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.2A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about 145C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130C, the regulator will restart again in the same manner as EN pin connects to logic HI.
FN7434.6 July 12, 2006
PWM Operation
The regulator operates the same way in the forced PWM or synchronized PWM mode. In this mode, the inductor current is always continuous and does not stay at zero. 9
EL7530
Thermal Performance
The EL7530 is available in a fused-lead MSOP10. Compared with regular MSOP10 package, the fused- lead package provides lower thermal resistance. The JA is 100C/W on a 4-layer board and 125C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow the equation below:
1 f Z = ---------------------2R 2 C 4
Power Good Output
The PG (pin 8) output is used to indicate when the output voltage is properly regulating at the desired set point. It is an open-drain output that should be tied to VIN or VCC through a 100k resistor. If no faults are detected, EN is high, and the output voltage is within ~5% of regulation, the PG pin will be allowed to go high. Otherwise, the open-drain NMOS will pull PG low.
Over a normal range of R2 (~10-100k), C4 will range from ~470-4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set point. The equation below shows the pole frequency relationship:
1 f P = --------------------------------------2 ( R 1 R 2 )C 4
Output Voltage Selection
Users can set the output voltage of the variable version with a resister divider, which can be chosen based on the following formula:
R 2 V O = 0.8 x 1 + ------ R 1
Layout Considerations
The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: 1. Separate the Power Ground ( ) and Signal Ground ( i); connect them only at one point right at the pins 2. Place the input capacitor as close to VIN and PGND pins as possible 3. Make the following PC traces as small as possible: from LX pin to L from CO to PGND 4. If used, connect the trace from the FB pin to R1 and R2 as close as possible 5. Maximize the copper area around the PGND pin 6. Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7530 Application Brief.
Component Selection
Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. We recommend 10F to 22F multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5H to 2.2H for the inductor. The RMS current present at the input capacitor is decided by the following formula:
V O x ( V IN - V O ) I INRMS = ----------------------------------------------- x I O V IN
This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as:
( V IN - V O ) x V O I IL = ------------------------------------------L x V IN x f S
L is the inductance fS the switching frequency (nominally 1.4MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 2A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the Typical Application Diagram). The phase-lead capacitor creates additional phase margin in the control loop 10
FN7434.6 July 12, 2006
EL7530 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY SYMBOL A A1 A2 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. C 6/99
E
E1
PIN #1 I.D.
b c D
B
1 (N/2)
E E1 e
e C SEATING PLANE 0.10 C N LEADS b
H
L L1 N
0.08 M C A B
NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H".
L1 A c SEE DETAIL "X"
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN7434.6 July 12, 2006

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